(1) Field of the Invention
The invention relates to a method of fabricating silicon structures, and more particularly, to the formation of narrow and wide shallow trench isolations with different depths to eliminate isolation oxide dishing problems.
(2) Description of the Prior Art
The use of shallow trench isolation (STI) for the formation of integrated circuit isolations has grown in the art due to the reduced surface area and improved topology of STI when compared to traditional local oxidation of silicon (LOCOS) schemes. One problem that is encountered in the use of STI is oxide dishing. Oxide dishing occurs, in part, due to pad deformation in the chemical mechanical polish (CMP) process used to planarize the STI structures. It is called dishing because the STI isolation oxide takes on the shape of a dish as the oxide in the trench is thinned by the CMP process. Dishing is especially pronounced on large or wide STI structures because the isolation oxide over these trenches is typically thinner than the oxide deposited over narrow trenches due to topological effects. Narrower STI structures demonstrate little or no dishing.
Referring to FIG. 1, a cross-section of a partially completed prior art integrated circuit is shown. A silicon substrate 10 is shown. A pad oxide layer 19 overlies the silicon substrate 10. A silicon nitride layer 20 overlies the pad oxide layer 19 as a polishing stop. Two narrow trenches 14 and one wide trench 18 have been etched into through the pad oxide layer 19 and the silicon nitride layer 20 and into the surface of the silicon substrate 10. The trenches have a common depth of LI because all were formed by the same reactive ion etch (RIE) process.
Referring to FIG. 2, an isolation oxide layer 22 has been deposited overlying the silicon nitride layer 20 and filling the trenches. Note how the topology of the trenches affects the topology of the isolation oxide layer 22. Where the isolation oxide layer 22 overlies the narrow trenches 14, it is relatively thick. Conversely, the isolation oxide layer 22 is relatively thin overlying the wide trench 18.
Referring to FIG. 3, the result of the chemical mechanical polish (CMP) is shown. The isolation oxide layer 22 has been polished down to the top surface of the silicon nitride layer 20 to complete the shallow trench isolations. Following the polish, however, significant dishing 24 is seen over the wide trench 18. This dishing 24 can cause increased current leakage and decreased gate oxide voltage breakdown. These problems at the active area interface reduce device yield.
Several prior art approaches disclose methods to create trenches having different depths into the substrate. U.S. Pat. No. 5,776,817 to Liang teaches a method to form trenches of different depths comprising: forming sacrificial refractory metal layers of different thickness, annealing the metal layers to create metal silicide layers of different depths into the underlying silicon substrate, and then removing the refractory metal and silicide layers to reveal trenches of different depths. U.S. Pat. No. 5,814,547 to Chang discloses a process to etch trenches using a microloading effect to cause the trenches to be etched to different depths. U.S. Pat. No. 5,851,928 to Cripe et al discloses a process to etch features of different depths in a single wet isotropic etching step by using a mask layer with different sized openings. U.S. Pat. No. 5,157,003 to Tsuji et al teaches a process to etch trenches of different depths. Selective exposure of phenol resin positive photoresist is used to define etching areas. Two etching steps are performed to form shallow trenches of two different depths.